Increasing capability and functionality, as well as falling prices, have driven electronic designers to use programmable logic devices (PLDs) in a wide variety of designs. Examples of PLDs commonly used include field programmable gate array (FPGA) devices, complex programmable logic devices (CPLDs), application specific integrated circuits (ASICs), and the like.
In many circuit designs, PLDs are implemented to communicate signals to and/or receive signals from other electronic components. Accordingly, the logic of the PLDs may be programmed so that certain contacts of the PLD are “assigned” to corresponding contacts of an electronic component such that the assigned contact receives signals from and/or provides signals to the corresponding contact of the electronic component via a conductive trace routed between the contact of the PLD and the contact of the electronic component.
Conventionally, the contact assignments (i.e., “pin assignments”) of electronic components differ by vendor. As a result, electronic systems implementing common electronic components typically are designed to maximize the footprint density of the electronic component as opposed to providing for the optimum breakout of the contacts of the electronic components. This emphasis on footprint density to the detriment of optimum breakout efficiency may not be perceived as a serious concern in low-contact-count component designs as the contact mapping between components typically is relatively simple. However, with the advent of high-density, multiple layer designs, inefficient mapping of contacts of PLDs to other electronic components, such as application specific integrated circuits (ASICs), has serious ramifications for the effective design and operation of such complex designs.
In view of the foregoing, it would be desirable to provide a technique that provides improved contact mapping of the contacts of a PLD to one or more other electronic components.